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Packard Bell 660 M/Board

660 Motherboard Diagram

Installing a video expansion card will automatically disable the on board video controller.


  • Battery : Socketed 3 volt Lithium coin cell battery at location BT5G1.
  • BIOS : Flash EEPROM - AMI BIOS.66MHz maximum bus speed.
  • Bus Architecture : PCI / ISA based system bus.
  • Cache : 16KB Level 1 Cache.End User units with the PB660 motherboard have a special CELP socket for an upgradeable COAST Cache module.
  • Chipset : VL82C593PSFC2 PCI / Cache / Memory Controller
    • PCI064B Super I/O Controller
    • S82378ZB System Controller
    • VL82C592PSFC2 Local Bus Extension
    • VL82C591PSFC3 PCI IDE Bridge
  • CPU : Intel Pentium Processor 75MHz-133MHz.Uses Type 7 Zero Insertion Force (ZIF) CPU Socket.
  • Interfaces :
    • 1 DB-9 Serial port for COM1
    • 1 DB-25 Parallel port
    • 1 PS/2 Keyboard port
    • 1 PS/2 Mouse port
    • 1 15 pin VGA
  • RAM : 8MB installed standard / 128MB maximum. Uses 4/8/16/32MB 72-pin SIMMs, 60 or 70ns, EDO or Fast Page RAM. Supports only non-parity DRAM.
  • UART : Two 16C550A Compatible chips.
  • Video : Onboard Cirrus Logic 5446 video chipset.
  • Video : RAM 2MB onboard.


J5K2 Cmos/Password1-2
CMOS Normal
Clear CMOS
Password Enabled
Password Disabled
J9C1 Recover BIOS1-2
J4K1 ISA Clock Speed Overide  1-2
1/3 PCI Clock
1/4 PCI Clock
J4K1 CMOS Setup Access4-5
Access Denied
J6A2 Processor Voltage1-2
Standard Voltage 3.3v
J5J1 Host Bus Speed1-2, 4-5
1-2, 5-6
2-3, 4-5
J5J2 CPU Clock Ratio1-2, 4-5
2-3, 4-5
2-3, 5-6
x 1.5
x 2.0
x 2.5


This 3V Lithium clip in battery is replaceable with a CR2032 battery.

Cache Upgrade

End user units include a special CELP socket for an upgradeable COAST Cache module.

There are two COAST module configurations supported:

1. Modules configured with 32k x 64 asynchronous SRAM with a 5v 8k x 8 SRAM Tag SRAM. Eight 32k x 8 3.3v srams are used for the Data rams (all are contained on the COAST module).

2. Modules configured with 32k x 64 burst or pipelined burst with either four 32k x 16 or two 32k x 32 (no parity) srams (also located on the COAST module).

Commercial units have 256KB of Cache soldered on board which is notupgradeable.

CPU Upgrades

This motherboard can accommodate the following CPUs:

  • Intel Pentium 75 MHz
  • Intel Pentium 90 MHz
  • Intel Pentium 100 MHz
  • Intel Pentium 120 MHz
  • Intel Pentium 133 MHz
  • Intel Pentium 150 MHz
  • Intel Pentium 166 MHz
  • Intel Pentium 200 MHz

Uses the 321-pin Type 7 Zero Insertion Force (ZIF) CPU socket.
Supports the Pentium OverDrive Processor.
Not keyboard switchable.
Disable cache to slow down the system.

Clock Speed (J5J1) CPU Multiplier (J5J2) Host Bus Speed CPU Speed 
1-2, 4-51-2, 4-5(x 1.5)50 MHz75 MHz
1-2, 5-61-2, 4-5(x 1.5)60 MHz90 MHz
2-3, 4-51-2, 4-5(x 1.5)66 MHz100 MHz
1-2, 5-62-3, 4-5(x 2.0)60 MHz120 MHz
2-3, 4-52-3, 4-5(x 2.0)66 MHz133 MHz
1-2, 5-62-3, 5-6(x 2.5)60 MHz*150 MHz
2-3, 4-52-3, 5-6(x 2.5)66 MHz*166 MHz
2-3, 4-51-2, 5-6(x 3.0)66 MHz**200 MHz

*Socket 7 only
** Requires Socket 7, and a flash BIOS update to 1.00.04.CP1R.

RAM Upgrades

Uses 4/8/16/32 MB 72-pin SIMMs, 60 or 70ns EDO or Fast Page Mode RAM.Supports only non-parity DRAM.

1. Bank by bank support for EDO or Fast Page Mode DRAM with automatic presence detect for EDO DRAM.60ns EDO required for 66 MHz bus speeds, and 70ns EDO required for 50 & 60 MHz bus speed.70ns Fast Page Mode required for 50, 60, and 66 MHz bus speeds.EDO and Fast Page Mode can be mixed in separate banks.

2. Four 32-bit SIMM sockets accept 4MB, 8MB, 16MB, 32MB in either single or double sided configurations.SIMMs must be added in pairs.SIMM sockets can be populated in any order.ONE or more SIMMs may be located under the peripheral bay in the Packard Bell "all-in-one" (Spectria) chassis.

3. Bank 0 will be populated as the default from the factory.

4. No configuration jumpers: BIOS detects memory size, and memory type (EDO or Fast Page Mode).

5. Memory voltage requirements: 5V.

Video Memory Upgrade

The PB660 uses CL-5446 Video Drivers.The PB660 has 2MB video memory and is not upgradeable further.